This invention relates to a semiconductor memory device, and to an associated semiconductor memory device fabrication process. More particularly, the present invention pertains to a nonvolatile memory device capable of storing data in accordance with a change in the polarization state caused by a change in the distribution of carriers occurring in a capacitor.
Dynamic random access memory (DRAM), one of the semiconductor memory devices, has been used widely. A typical DRAM is made up of a great number of unit memory cells and each unit memory cell consists of a single capacitor and a switching MOS transistor. A voltage is extracted from a bit line in the form of a signal which represents a particular item of data in a "0"- or "1"-state written into a capacitor of a selected memory cell. The extracted voltage is amplified by a sense amplifier and is read out. In DRAM, the destruction of data occurs by the act of reading the data (destructive read), so refresh must be performed to write such vanished data back to the same location. Additionally, the DRAM has the problem that its stored data volatilizes when the power is turned off.
A flash electrically erasable programmable read-only memory (EEPROM) of a nonvolatile type has some advantages over the DRAM; for example, it has the ability of holding data stored in it without the need for a power supply. A memory cell of a typical EEPROM is formed by a single MOSFET having a so-called stacked gate structure characterized by a floating gate electrode arranged between a control gate electrode and a semiconductor body. An EEPROM of this type stores data in accordance with a change in the threshold voltage of MOSFET depending on the amount of charge stored within the floating gate. In a data write operation, a high voltage is applied to a drain region so as to generate hot carriers, and the generated hot carriers surmount the energy barrier. Then these carriers (e.g., electrons) are injected from the semiconductor body to the floating gate. Alternatively, it is possible to write data by applying to a gate oxide a high electric field, whereby an F-N (Fowler-Nordheim) tunnelling current flows through the gate oxide so that carriers are likewise injected into the floating gate. Conversely, in order to erase stored data, a high electric field in an opposite direction to the above is applied to the gate oxide, so as to shift the injected carriers from the floating gate to the semiconductor body by means of F-N tunnelling. This technique, however, is required to produce a high electric field within a memory cell, thereby making it difficult to accomplish lower-voltage write/erase operations. Further, it is necessary to exchange carriers between the floating gate electrode and the outside when executing a write or erase operation. This is an obstacle to the realization of low power operations. Although a conventional flash EEPROM requires no refresh operations, it takes a prohibitively longer length of time for write/erase operations as compared with a DRAM.
The frequent passage of carriers through a silicon oxide layer forming a gate dielectric layer may cause silicon oxide breakdown. This issue is discussed by I. C. Chen et. al. in a paper entitled "Oxide breakdown dependence on thickness and hole current," International Electron Device Meeting, Technical Digest p. 660-663. This paper suggests that the silicon oxide breakdown is due to a positive feedback effect induced by hole generation and trapping at localized spots. This paper also points out that hole generation requires large electron energy, which decreases with decreasing the film thickness of the silicon oxide. Therefore, ultra thin silicon oxides have superior reliability.
Another type of nonvolatile memory is a nonvolatile RAM (NV-RAM). A typical NV-RAM memory cell is made up of a single MFS (metal-ferroelectric-semiconductor) FET employing a ferroelectric layer as a gate dielectric layer. The state of ion polarization in the ferroelectric layer varies with the application direction of an electric field, so that the threshold voltage of a MFSFET likewise varies. Such a change is used to store data.
Japanese Patent Application Gazette No. 4-97564 shows a semiconductor memory device. In accordance with this prior art technique, an ion polarization in a ferroelectric layer is made to look as if it is replaced with a polarization by an "electric dipole". This semiconductor memory device is built up employing a FET structure having a drain region and a source region each formed on a Si substrate surface region and a gate electrode (see FIG. 19a). Sandwiched between the gate electrode and the Si substrate is a capacitor made up of a plurality of layers. In this capacitor, plural active regions, arranged between dielectric layer barriers, correspond to respective unit crystal lattices of the ferroelectric layer. As shown in FIG. 19b, depending on the applied electric field, carriers comes and goes through a tunnelling barrier provided within each active region. As a result, the carriers are localized to store data.
The above-described electric dipole structure provides some advantages. For example, since a tunnelling layer through which carriers migrate is considerably thin, this reduces the amount of energy necessary for a carrier to migrate. As a result, breakdown due to the passage of carriers hardly occurs. However, the magnitude of dipole moment induced by the electric dipole is a product of the magnitude of charge times the positive-to-negative charge distance. So, even if carriers are localized through a very thin tunnelling layer, it is impossible to produce a large dipole moment. Therefore, the change in electric field produced by the electric dipole is too small to read data from changes in the characteristic of current flowing between the underlying drain and source regions. If the film thickness of the tunnelling layer is increased, then a voltage required for performing a data write (or erase) operation becomes high. As a result, power consumption is increased. Additionally, the amount of energy, too, increases and silicon oxide breakdown may occur.